1. Field of the Invention
This invention relates to semiconductor memory devices, and more particularly, to a read method for reading data from a high-density semiconductor read-only memory (ROM) device.
2. Description of Related Art
A ROM device is a nonvolatile semiconductor memory device which is widely utilized in computer-based systems and various other intelligent electronic devices for permanent storage of routinely or frequently used program codes therein. The data stored in a ROM device can be retained permanently even after the power is turned off.
ROM devices can be constructed in various manners. One widely used type uses an array of MOSFETs to serve as the memory cells. In the mask programming process, an impurity element is doped into the channel of a selected group of these MOSFET-based memory cells that are to be set to a permanently-ON state, while the other cells that are to be set to a permanently-OFF state are undoped. The permanently-ON state represents the storage of a first binary value, for example 0; while the permanently-OFF state represents the storage of a second binary value, for example 1 as shown in FIG. 1, sections between these word lines 10 and bit lines 12 are the locations where the memory cells of the ROM device are defined, each intersection corresponding to one memory cell. In the mask programming process, the channel regions of these MOSFET-based memory cells, as designated by the reference numeral 14, are selectively doped with an impurity element to set the associated memory cells to a permanently-ON state representing the permanent storage of a first binary value, for example 0, with the undoped memory cells being set to a permanently-OFF state representing the permanent storage of a second binary value, for example 1. In the case of FIG. 1, for example, the dotted boxes those memory cells that are set to a permanently-ON state.
FIG. 2 is an equivalent circuit diagram of a group of the MOSFET-based memory cells in the conventional ROM device. As shown, the ROM device includes a plurality of parallel-spaced word lines WL1, WL2, WL3 and a plurality of parallel-spaced bit lines BL1, BL2, BL3, BL4 intercrossing the word lines WL1, WL2, WL3. The data stored in a particular memory cell in the ROM device can be read out by applying a suitable voltage (referred to as addressing voltage) to the associated word line of that memory cell.
In the case of FIG. 2, assume the memory cells 22 and 26 are set to a permanently-ON state (representing the storage of a first binary value, for example 0) while the memory cell 24 is set to a permanently-OFF state (representing the storage of a second binary value, for example 1). The memory cell 22 has its gate connected to the word line WL2 and its two source/drain regions connected respectively to the bit lines BL2 and BL3; while the memory cell 24 has its gate connected to the word line WL1 and its two source/drain regions connected respectively to the bit lines BL3 and BL4.
To read the data stored in the memory cell 22, a high potential is applied to the associated word line WL2, while a high potential is applied to the bit line BL2 and a ground potential is applied to the bit line BL3. Since the memory cell 22 is set to a permanently-ON state, its source-to-drain path (channel) is in a conductive state, allowing the high potential on the bit line BL2 to be pulled down by the ground potential on the bit line BL3, thus inducing a current to flow from the bit line BL2 through the memory cell 22 to the bit line BL3, as indicated by the arrow 25 in FIG. 2. As a result, by detecting the current in the bit line BL2 (this current is hereinafter referred to as data current), the external circuit can determine that a binary value 0 is being read out from the memory cell 22.
In the forgoing case, however, it is required that a high potential be also applied to the neighboring bit line BL1 since the neighboring memory cell 26 is also set to a permanently-ON state; otherwise, an undesired current will be also induced to flow from the bit line BL2 to the bit line BL1, resulting in erroneous data output from the bit lines.
To read the data stored in the memory cell 24, a high potential is applied to the associated word line WL1, while a high potential is applied to the bit line BL3 and a ground potential is applied to the bit line BL4. Since the memory cell 22 is set to a permanently-OFF state, its source-to-drain path is in a nonconductive state, thus allowing the high potential on the bit line BL3 to be isolated from the ground potential on the bit line BL4. As a result, by detecting the current on the bit line BL3 (in this case, no current), the external circuit can determine that a binary value 1 is being read out from the memory cell 24.
One drawback to the foregoing ROM device is that it requires the use of three lines (one word line and two bit lines) at the same time to address each of the memory cells in order to prevent the undesired current flow to the neighboring bit line associated with the neighboring memory cell that is not currently addressed.
Moreover, since the breakthrough voltage at the junction between each bit line and the channel of the associated memory cells is about 3.0 V (volt), the addressing voltage applied to the word and bit lines during the read operation should be restricted to below 3.0 V. This low addressing voltage would often make the read operation unreliable.
Still moreover, the bit lines of the conventional ROM device are formed from highly-doped diffusion region, which typically have a resistance of 100 .OMEGA./.quadrature. (ohm per square). This resistance is still considered too high to make the data current in the bit lines large enough for reliable detection. The performance of the read operation is thus low.